Herner et al., U.S. patent application Ser. No. 10/955,549 filed Sep. 29, 2004 (which corresponds to US Published Application 2005/0052915 A1), hereby incorporated by reference, describes a three dimensional memory array in which the data state of a memory cell is stored in the resistivity state of the polycrystalline semiconductor material of a pillar shaped semiconductor junction diode. A subtractive method is used to fabricate such pillar diode devices. This method includes depositing one or more silicon, germanium or other semiconductor material layers. The deposited semiconductor layer or layers are then etched to obtain semiconductor pillars. A SiO2 layer can be used as a hard mask for the pillar etching and removed afterwards. Next, SiO2 or other gap fill dielectric material is deposited in between and on top of the pillars. A chemical mechanical polishing (CMP) or etchback step is then conducted to planarize the gap fill dielectric with the upper surface of the pillars.
For additional description of the subtractive pillar fabrication process, see Herner et al., U.S. patent application Ser. No. 11/015,824, “Nonvolatile Memory Cell Comprising a Reduced Height Vertical Diode,” filed Dec. 17, 2004 and U.S. patent application Ser. No. 11/819,078 filed Jul. 25, 2007.
However, in the subtractive method, for small diameter or width pillar type devices, care must be taken to avoid undercutting the pillar at its base during the etching step. Undercut pillar devices may be susceptible to falling over during subsequent processing. Furthermore, for smaller pillar devices, the height of the semiconductor pillar may be limited by thin and soft photoresist used as the etching mask, the oxide gap filling step presents a processing challenge when the aspect ratio of the openings between the pillars increases, and the CMP process or etchback of the gap fill layer may remove a significant thickness of the deposited semiconductor material.